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19-0619; Rev 0; 8/06
KIT ATION EVALU E AILABL AV
HDTV Anti-Aliasing Filters with Triple-Input Mux
General Description
The MAX7472/MAX7473 triple-channel anti-aliasing filters and buffers with triple-input mux are ideal for highdefinition (HD) and standard-definition (SD) television (TV) applications. Compatible with 1080i, 720p, 480p, and 480i scanning system standards as well as computer format signals, the MAX7472/MAX7473 support component video (Y PB PR, GsBR, and RGBHV) as well as composite (CVBS) and S-video (Y/C). The MAX7472/MAX7473 limit the input bandwidth for anti-aliasing and out-of-band noise reduction prior to digital conversion by an ADC or video decoder. The frequency response of the MAX7472/MAX7473 can be continuously varied in 256 linear steps from below SD response to beyond HD response through an I2C interface. The adjustable cutoff frequency allows filter optimization for sampling rate and noise reduction. The MAX7472/MAX7473 also include 3:1 multiplexers for selection of three complete sets of video inputs through the I2C interface. The MAX7472/MAX7473 drive a 2VP-P video signal into a standard 150 load. The inputs are AC-coupled and the outputs can be either DC- or AC-coupled. The MAX7472 has a gain of 0dB and the MAX7473 has a gain of +6dB. Both devices are available in a 28-pin TQFN package and are fully specified over the uppercommercial (0C to +85C) temperature range.
Features
o Continuously Variable Anti-Aliasing Filter 5MHz to 34MHz in 256 Steps o 3:1 Input Mux on Each Video Filter o Supports All Standard Video and Computer Input Formats 480i, 480p, 720p, 1080i QVGA, VGA, SVGA, XGA, SXGA, UXGA Y PB PR, GsBR, RGBHV, Y/C, CVBS o Accepts Any Input Sync Format Sync on Y, Sync on G, External Sync (Positive or Negative) Sync on All Channels o Buffered Outputs Drive Standard 150 Video Load 0dB (MAX7472) +6dB (MAX7473) o DC- or AC-Coupled Outputs o Single +5V Analog and +3.3V Digital Supplies o 5mW Power-Down Mode o Lead (Pb)-Free 28-Pin TQFN Package
MAX7472/MAX7473
Ordering Information
PART PIN-PACKAGE 28 TQFN-EP* PKG CODE T2855-8 BUFFER GAIN (dB) 0
Applications
HDTV (LCD, PDP, DLP, CRT) Set-Top Boxes Personal Video Recorders Home Theaters
MAX7472UTI+
MAX7473UTI+** 28 TQFN-EP* T2855-8 +6 Note: All devices are specified over the 0C to +85C operating temperature range. +Indicates lead-free packaging. *EP = Exposed pad. **Future product--contact factory for availability.
Pin Configuration
OUT1 OUT2 OUT3 AVDD DVDD 16 AVDD 21 AVDD 22 A0 23 20 19 18 17 15 14 13 12 SCL SYNCC SYNCB SYNCA DGND INC3 INB3 SDA 11 10 EP* 9 8 1 INC1 2 AGND 3 INA2 4 INB2 5 INC2 6 AGND 7 INA3
TOP VIEW
Typical Operating Circuit appears at end of data sheet.
A1 24 AGND 25 AGND 26 INA1 27 INB1 28 +
MAX7472 MAX7473
TQFN 5mm x 5mm *EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
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HDTV Anti-Aliasing Filters with Triple-Input Mux MAX7472/MAX7473
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +4V AGND to DGND.....................................................-0.3V to +0.3V INA_, INB_, INC_ to AGND........................................................... ............................-0.3V to the lower of (AVDD + 0.3V) and +6V OUT_ to AGND......-0.3V to the lower of (AVDD + 0.3V) and +6V SYNC_, A_ to AGND..................................................................... ...............................-0.3V to the lower of (AVDD + 0.3V) and +6V SCL, SDA to DGND .................................................-0.3V to + 6V Maximum Current into Any Pin (except AVDD, DVDD, and OUT) ...................................50mA Continuous Power Dissipation (TA = +70C) 28-Pin TQFN (derate 34.5mW/C above +70C) ........2758mW Operating Temperature Range.............................. 0C to +85C Storage Temperature Range ............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +5V 5%, DVDD = 2.7V to 3.6V, RLOAD = 150 to AGND, CIN = 0.1F, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS HD: f = 100kHz to 30MHz, relative to 100kHz (Note 1) Filter Passband Response APB SD: f = 100kHz to 5.75MHz, relative to 100kHz (Note 2) HD: f = 74MHz (Note 1) SD: f = 27MHz (Note 2) HD: 100kHz to 30MHz, relative to 100kHz (Note 1) SD: 100kHz to 5.75MHz, relative to 100kHz (Note 2) HD: channel to channel, 100kHz to 2MHz (Note 1) Group-Delay Matching tG(MATCH) SD: channel to channel, 100kHz to 500kHz (Note 2) -3dB, bypass mode, independent of filter setting dG d SNR HDIST VDIST 5-step modulated staircase (Note 2) 5-step modulated staircase (Note 2) Output signal (2VP-P) to RMS noise (100kHz to 30MHz) (Note 1) Deviations in a line with an 18s, 100 IRE bar, 1 line = 63.5s (Note 2) Deviations in 130 lines with 18s, 100 IRE bars (Note 2) MIN -3 TYP -0.6 0.1 57 63 20 ns 15 5 ns 1.5 100 0.25 0.25 69 0.3 0.3 MHz % Degrees dB % % MAX +1 dB 1.0 dB UNITS
Filter Stopband Attenuation
ASB
Group-Delay Deviation
tG
Bypass Frequency Response SD Differential Gain SD Differential Phase Signal-to-Noise Ratio SD Line-Time Distortion SD Field-Time Distortion
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HDTV Anti-Aliasing Filters with Triple-Input Mux
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +5V 5%, DVDD = 2.7V to 3.6V, RLOAD = 150 to AGND, CIN = 0.1F, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Clamp Settling Time Minimum Functional Input Sync Amplitude Low-Frequency Gain Low-Frequency Gain Matching Maximum Input Voltage Amplitude Maximum Output Voltage Amplitude Output Clamping Level Variation Mux Crosstalk Channel-to-Channel Isolation Power-Supply Rejection Ratio DIGITAL INPUTS (A1, A0, SYNC_) Input Logic High Voltage Input Logic Low Voltage Input Leakage Current Input Capacitance DIGITAL INPUTS (SDA, SCL) Input Logic High Voltage Input Logic Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (SDA) Output Logic Low Voltage Tri-State Leakage Current Tri-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Range Digital Supply Voltage Range Analog Supply Current Digital Supply Current AVDD DVDD IAVDD IDVDD Normal operation, no load Power-down mode, no load 4.75 2.7 5 3.3 180 1 25 5.25 3.6 200 1.5 V V mA A VOL IL COUT ISINK = 3mA VIN = 0 to DVDD 0.1 6 0.4 10 V A pF VIH VIL VHYST IIN CIN VIN = 0 to DVDD 0.05 x DVDD 0.1 6 10 0.7 x DVDD 0.3 x DVDD V V V A pF VIH VIL IIN CIN VIN = 0 to DVDD 1 6 2.0 0.8 10 V V A pF PSRR TA = +25C, MAX7472 (Note 1) TA = +25C, MAX7473 (Note 1) 100kHz MAX7472 MAX7473 DC to 30MHz (Notes 1, 4) -80 62 50 SYMBOL CONDITIONS To 1% with 100 IRE step (Note 3) Positive Negative 125 -0.5 5.5 0 6 0.05 2.4 1.2 2.4 120 +0.5 6.5 MIN TYP 350 650 MAX UNITS H mV dB dB VP-P VP-P mV dB dB dB
MAX7472/MAX7473
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HDTV Anti-Aliasing Filters with Triple-Input Mux MAX7472/MAX7473
TIMING CHARACTERISTICS
(AVDD = +5V 5%, DVDD = 2.7V to 3.6V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Figure 1)
PARAMETER Serial Clock Frequency Bus Free Time Between STOP (P) and START (S) Conditions Hold Time (Repeated) START (Sr) Condition SCL Pulse-Width Low SCL Pulse-Width High Setup Time for a Repeated START (Sr) Condition Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals, Receiving Fall Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Signal, Transmitting Setup Time for STOP (P) Condition Capacitive Load for Each Bus Line Pulse Width of Spikes Suppressed by the Input Filter SYMBOL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tf tSU;STO Cb tSP (Note 7) 0 (Note 6) (Note 5) After this period, the first clock pulse is generated CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 0 0 20 + 0.1Cb 0.6 400 50 300 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s s ns ns ns ns s pF ns
The filter passband edge is set to code 255. The filter passband edge is set to code 40. 1H is the total line period, depending on the video standard. For NTSC, this is 63.5s, for HDTV, the line period is 29.64s. The clamp level is at the sync tip for signals with sync pulses, and is at the blanking level otherwise. A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL's falling edge. Note 6: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3VDD and 0.7VDD. Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Note 1: Note 2: Note 3: Note 4: Note 5:
SDA tBUF
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
tSP
tr
SCL
tHD;STA S
tHD;DAT
tHIGH
tSU;STA Sr
tSU;STO P S
Figure 1. 2-Wire Serial-Interface Timing Diagram
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HDTV Anti-Aliasing Filters with Triple-Input Mux
Typical Operating Characteristics
(AVDD = +5V, DVDD = 3.3V, RLOAD = 150 to GND, CIN = 0.1F, TA = +25C.)
MAX7472/MAX7473
FREQUENCY RESPONSE (MAX7472)
MAX7472/73 toc01
FREQUENCY RESPONSE (MAX7473)
0 -10 RESPONSE (dB) CODE 40 -20 -30 -40 -50 -60 -70 CODE 90 CODE 220 CODE 255
MAX7472/73 toc02
PASSBAND FLATNESS (MAX7472)
0.5 0 RESPONSE (dB) -0.5 -1.0 CODE 90 -1.5 -2.0 -2.5 -3.0 CODE 220 CODE 255 CODE 40
MAX7472/73 toc03
10 0 -10 RESPONSE (dB) -20 -30 -40 -50 -60 -70 -80 0.1 1 10 100 CODE 90 CODE 255 CODE 40 CODE 220
10
1.0
1000
0.1
1
10
100
1000
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
PASSBAND FLATNESS (MAX7473)
MAX7472/73 toc04
GROUP DELAY
80 70 60 DELAY (ns) 50 40 30 HD SD
MAX7472/73 toc05
2T RESPONSE (1 IRE = 7.14mV)
MAX7472/73 toc06
7.0 6.5 6.0 RESPONSE (dB) 5.5 5.0 4.5 4.0 3.5 3.0 0.1 1 10 CODE 220 CODE 255 CODE 40 CODE 90
90
20 10 0 100 0.1 1 10 100 100ns/div
FREQUENCY (MHz)
FREQUENCY (MHz)
MODULATED 12.5T RESPONSE
DIFFERENTIAL GAIN (%) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3
MAX7472/73 toc07
DIFFERENTIAL GAIN
MAX7472/73 toc08
-3dB FREQUENCY vs. CONTROL CODE
MEASURED CUTOFF FREQUENCY (MHz)
MAX7472/73 toc09
35 30 25 20 15 10 5
DIFFERENTIAL PHASE ()
DIFFERENTIAL PHASE
0.2 0.1 0 -0.1 -0.2 1 2 3 4 5 6 7
400ns/div
0
51
102 153 CONTROL CODE
204
255
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HDTV Anti-Aliasing Filters with Triple-Input Mux MAX7472/MAX7473
Typical Operating Characteristics (continued)
(AVDD = +5V, DVDD = 3.3V, RLOAD = 150 to GND, CIN = 0.1F, TA = +25C.)
BYPASS-MODE FREQUENCY RESPONSE
MAX7472/73 toc10
BYPASS-MODE GROUP DELAY
MAX7472/73 toc11
10 5 0 RESPONSE (dB) -5 -10 -15 -20 -25 -30 -35 -40 0.1 1 10 100 MAX7473 MAX7472
20
16 DELAY (ns)
12
8
4
0 1000 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz)
Pin Description
PIN 1 2, 6, 25, 26 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18, 20, 22 NAME INC1 AGND INA2 INB2 INC2 INA3 INB3 INC3 DGND SYNCA SYNCB SYNCC SCL SDA DVDD OUT3 AVDD FUNCTION Channel C Input 1. AC-couple INC1 with a series 0.1F capacitor. Analog Ground. Connect all AGND pins to the ground plane. See the Power-Supply Bypassing and Layout Considerations section. Channel A Input 2. AC-couple INA2 with a series 0.1F capacitor. Channel B Input 2. AC-couple INB2 with a series 0.1F capacitor. Channel C Input 2. AC-couple INC2 with a series 0.1F capacitor. Channel A Input 3. AC-couple INA3 with a series 0.1F capacitor. Channel B Input 3. AC-couple INB3 with a series 0.1F capacitor. Channel C Input 3. AC-couple INC3 with a series 0.1F capacitor. Digital Ground. See the Power-Supply Bypassing and Layout Considerations section. Channel A External Sync Input. Connect to ground if not used. Channel B External Sync Input. Connect to ground if not used. Channel C External Sync Input. Connect to ground if not used. I2C-Compatible Serial Clock Input I2C-Compatible Serial Data Input/Output Digital Power Supply. Bypass to DGND with a 0.1F capacitor. See the Power-Supply Bypassing and Layout Considerations section. Video Output 3. OUT3 can be either AC- or DC-coupled. Analog Power Supply. Bypass each AVDD input to AGND using a 0.1F capacitor. See the PowerSupply Bypassing and Layout Considerations section.
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HDTV Anti-Aliasing Filters with Triple-Input Mux
Pin Description (continued)
PIN 19 21 23 24 27 28 -- NAME OUT2 OUT1 A0 A1 INA1 INB1 EP FUNCTION Video Output 2. OUT2 can be either AC- or DC-coupled. Video Output 1. OUT1 can be either AC- or DC-coupled. Address Bit 0 Address Bit 1 Channel A Input 1. AC-couple INA1 with a series 0.1F capacitor. Channel B Input 1. AC-couple INB1 with a series 0.1F capacitor. Exposed Pad. The exposed pad is located on the package bottom and is internally connected to AGND. Connect EP to the analog ground plane. Do not route any PC board traces under the package. See the Power-Supply Bypassing and Layout Considerations section.
MAX7472/MAX7473
Detailed Description
The MAX7472/MAX7473 are complete video anti-aliasing solutions ideal for fixed-pixel HDTV display technologies such as plasma and LCD, which digitize the input video signal and then scale the resolution to match the native pixel format of the display. With a software-selectable corner frequency ranging from 5MHz to 34MHz, the MAX7472/MAX7473 support both SD and HD video signals including 1080i, 720p, 720i, 480p, and 480i. Higher bandwidth computer resolution signals are also supported. Integrated lowpass filters limit the analog video input bandwidth for anti-aliasing and out-of-band noise reduction prior to sampling by an ADC or video decoder. By allowing the corner frequency to be adjusted from below SD resolution to beyond HD resolutions in 256 steps, the filter's corner frequency can be optimized dynamically for a specific input video signal and the sampling frequency of the ADC or video decoder. The MAX7472/MAX7473 provide a filter-bypass mode to support applications requiring a passband greater than 34MHz. An I2C interface allows a microcontroller to configure the MAX7472/MAX7473s' performance and functionality
including the mux, the clamp voltage, the filter's corner frequency, the sync source (internal/external), and filter bypassing. The Typical Operating Circuit shows the block diagram and typical external connections of the MAX7472/ MAX7473.
Sync Detector and Clamp Levels
The MAX7472/MAX7473 use a video clamp circuit to establish a DC offset for the incoming video signal after the AC-coupling capacitor. This video clamp sets the DC bias level of the circuit at the optimum operating point. The MAX7472/MAX7473 support both internal and external sync detection. Selection of internal vs. external detection is achieved by programming the command byte (see Table 3). After extracting the sync information from channel 1 or an external sync (SYNCA, SYNCB, or SYNCC), the MAX7472/MAX7473 clamp the video signal during the sync tip portion of the video. Select one of two possible clamp levels according to the input signal format. Use the low level when the input signal contains sync information such as Y (luma) or CVBS signals. Use the high level for bipolar signals such as C (chroma) or PB/PR. See Table 1.
Table 1. Clamp Levels
INPUT SIGNAL FORMAT Y PB PR GsBR CVBS Y C Y PB PR (sync on all signals) RGBHV CLAMP LEVEL CHANNEL 1 Low Low Low Low High CHANNEL 2 High High Low Low High CHANNEL 3 High High High Low High
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HDTV Anti-Aliasing Filters with Triple-Input Mux MAX7472/MAX7473
Component/Composite Selection The MAX7472/MAX7473 accept component or composite inputs. The sync detection path provides an additional selectable color burst filter to improve sync detection. External Sync Detection When filtering a video signal without embedded sync information, such as computer formats (RGBHV) with separate sync signals, use the external sync mode (see Table 3) and apply the horizontal sync source to the SYNCA, SYNCB, or SYNCC pin. The sync detector determines when the clamp circuit is turned on. The MAX7472/MAX7473 can detect positive or negative polarity external syncs with TTL logic levels. Use the I2C interface to program the polarity of the external sync signal.
erations, one of the most important being the sampling rate of the subsequent ADC or video decoder in the system. In oversampled systems, the sampling rate is significantly more than the desired passband response. The extra frequency span between the passband and the sampling rate contains noise that can be eliminated by setting the corner frequency of the filter to just pass the desired bandwidth. This results in a higher signalto-noise ratio of the overall system.
Filter Bypass The MAX7472/MAX7473 offer selectable filter bypassing that allows the input video signals to bypass the internal filters reaching the output buffers unfiltered. The filter-bypass mode is enabled/disabled through the command byte (see Table 3).
Output Buffer
Each output buffer can drive a 2VP-P signal into a 150 video load. The MAX7472/MAX7473 can drive a DC- or AC-coupled load. The output DC level is controlled to limit the DC voltage on the cable so that the blanking level of the video signal is always less than 1V, meeting the digital TV specification. As a result, output AC-coupling capacitors can be eliminated when driving a cable, thus eliminating the normal adverse effects caused by these capacitors such as line- and field-time distortion, otherwise known as droop. See the Output Considerations section for more information.
Filter
The internal video filter delivers an optimized response with a steep transition band to achieve a wide passband along with excellent stopband rejection. In addition, the filter is optimized to provide an excellent timedomain response with low overshoot.
Setting the Filter Frequency The frequency response (-3dB cutoff frequency) of the filter in the MAX7472/MAX7473 can be varied from less than the SD passband to beyond the HD passband in 256 linear steps through the I2C interface. Use the command byte to write to the Frequency register followed by the 8-bit data word that corresponds to the desired frequency. See Table 6.
The Frequency register sets the -3dB point. Set this frequency accordingly to achieve the desired flat passband response.
Optimizing the Frequency Response Select the frequency according to the resolution of the video-signal format. High-definition signals require higher bandwidth and standard-definition signals require less bandwidth. The actual bandwidth contained in the video signal is a function of the visual resolution of the signal. This bandwidth is typically less than what is indicated by the format resolution (1080i, 720p, 480p, and 480i). For more information on this topic, see Application Note 750: Bandwidth vs. Video Resolution on the Maxim website (www.maxim-ic.com). See Table 6. The frequency response can be optimized to improve the overall performance. There are a number of consid-
Gain Options The MAX7472 features an overall gain of 0dB, while the MAX7473 features an overall gain of +6dB. Use the +6dB option (MAX7473) when driving a back-matched cable. Use the 0dB option (MAX7472) when driving an ADC or video decoder with an input range the same as the input to the MAX7472. To add flexibility, the MAX7472 accepts input signals up to 2VP-P, twice the standard video-signal range. Output Clamp Level The MAX7472/MAX7473 output can be DC- or AC-coupled. The nominal output clamp level in the DC-coupled case depends on the clamp voltage setting and can be determined according to Table 2.
Table 2. Output Clamp Level
CLAMP SETTING Low High OUTPUT CLAMP LEVEL (mV) (typ) 100 100
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HDTV Anti-Aliasing Filters with Triple-Input Mux
As shown in the Sync Detector and Clamp Levels section, the low clamp level is used for signals with sync information and determines the voltage level of the sync tip, while the high clamp level is used for signals without sync information and sets the blanking level. The absolute voltage level of the output signal is relative to the output clamp level. A video signal containing sync information (i.e., CVBS or Y) is unipolar above the clamp level and conversely, a video signal without sync (i.e., PB, PR, or C) is bipolar around the clamp level. SCL facilitate bidirectional communication between the MAX7472/MAX7473 and the master at rates up to 400kHz. Once a command byte is written to the MAX7472/ MAX7473, the command interpreter changes the Control/Status register and the Channel Selection register accordingly. See the Control/Status Register and Channel-Selection Register sections for more information. The command interpreter also controls access to the Frequency register (see the Command Byte (Write Cycle) section). The MAX7472/MAX7473 are transmit/receive slave-only devices, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL. A master device communicates to the MAX7472/ MAX7473 by transmitting the proper address (see the Slave Address section) followed by a command and/or data words. Each transmit sequence is framed with a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. The SDA driver is an open-drain output, requiring a pullup resistor (2.4k or greater) to generate a logichigh voltage. Optional resistors (24) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot of the bus signals.
MAX7472/MAX7473
Multiplexers
The MAX7472/MAX7473 provide four 3:1 multiplexers programmable through the I2C interface to select which of three separate channels (channels A, B, C) is to be connected to each video input. The fourth multiplexer is used in conjunction with external sync detection and determines which channel's external sync is to be connected to the external sync input. See Table 3 and the Serial Interface section for more information on how to select a particular channel. After selecting a channel with a command byte, bits CS7 and CS6 of the Channel Selection register reflect the channel setting (Table 7).
Power-Down Mode
The MAX7472/MAX7473 include a power-down mode that reduces the supply current from 180mA (typ) to 1mA (typ) by powering down the analog circuitry. The I 2C interface remains active allowing the device to return to full-power operation. The clamp settling time (see the Electrical Characteristics table) limits the wake-up time of the MAX7472/MAX7473. After exiting the power-down mode, the MAX7472/MAX7473 resume normal operation using the settings stored prior to power-down. The command byte controls the powerdown and wake-up modes (see Table 3). A software reset sets the Control/Status register to its default conditions. The Frequency register and the Channel Selection register are not affected.
Bit Transfer Each SCL rising edge transfers 1 data bit. Nine clock cycles are required to transfer the data into or out of the MAX7472/MAX7473. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are read as control signals (see the START and STOP Conditions section). When the serial interface is inactive, SDA and SCL idle high. START and STOP Conditions A master device initiates communication by issuing a START condition (S), a high-to-low transition on SDA with SCL high (Figure 2). The master terminates transmission by a STOP condition (P) (see the Acknowledge Bit (ACK) and Not-Acknowledge Bit (NACK) section). A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 2). The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active. When a STOP condition or incorrect address is detected, the MAX7472/ MAX7473 then ignore all communication on the I2C bus until the next START or REPEATED START condition, minimizing digital noise and feedthrough.
Power-On Reset (POR)
The MAX7472/MAX7473 include a power-on reset (POR) circuit that resets the internal registers and I2C interface to their default condition (see Tables 4-7).
Serial Interface
The MAX7472/MAX7473 feature an I 2C-compatible, 2-wire serial interface consisting of a bidirectional serial data line (SDA) and a serial clock line (SCL). SDA and
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HDTV Anti-Aliasing Filters with Triple-Input Mux MAX7472/MAX7473
Early STOP Conditions The MAX7472/MAX7473 recognize a STOP condition at any point during transmission except when a STOP condition occurs in the same high pulse as a START condition (Figure 3). This condition is not a legal I2C format; at least one clock pulse must separate any START and STOP conditions. The MAX7472/MAX7473 discard any data received during a data transfer aborted by an early STOP condition. REPEATED START (Sr) Conditions An Sr condition is used to indicate a change in direction of data flow (see the Read Cycle section). Sr can also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX7472/MAX7473 serial interface supports continuous write operations with (or without) an Sr condition separating them. Acknowledge Bit (ACK) and Not-Acknowledge Bit (NACK) Successful data transfers are acknowledged with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX7472/MAX7473 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 4). To generate a not acknowledge, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse (ninth pulse) and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time. The MAX7472/MAX7473 generate an acknowledge bit when receiving an address or data by pulling SDA low during the ninth clock pulse. When transmitting data during a read, the MAX7472/MAX7473 do not drive SDA during the ninth clock pulse (i.e., the external pullups define the bus as a logic high) so that the receiver of the data can pull SDA low to acknowledge receipt of data. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address (Figure 5). When idle, the MAX7472/MAX7473
S
Sr
P
SCL
SDA
Figure 2. START/STOP Conditions
LEGAL STOP CONDITION SCL SDA STOP START SCL SDA
ILLEGAL STOP CONDITION
START
ILLEGAL STOP
Figure 3. Early STOP Conditions
S NOT ACKNOWLEDGE SDA ACKNOWLEDGE SCL 1 8 9
Figure 4. Acknowledge and Not-Acknowledge Bits
wait for a START condition followed by its slave address. The serial interface compares each address bit by bit, allowing the interface to power down and disconnect from SCL immediately if an incorrect address is detected. After recognizing a START condition followed by the correct address, the MAX7472/MAX7473 are ready to accept or send data. The least significant bit (LSB) of the address byte (R/W) determines whether the master is writing to or reading from the MAX7472/MAX7473 (R/W = 0 selects a write condition, R/W = 1 selects a read condi-
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HDTV Anti-Aliasing Filters with Triple-Input Mux
tion). After receiving the proper address, the MAX7472/MAX7473 (slave) issue an ACK by pulling SDA low for one clock cycle. The MAX7472/MAX7473 slave address consists of 5 fixed bits A6-A2 (set to 10010) followed by 2 pin-programmable bits A1 and A0. The most significant address bit (A6) is transmitted first, followed by the remaining bits. Addresses A1 and A0 can also be driven dynamically if required, but the values must be stable when they are expected in the address sequence. ACK. The MAX7472/MAX7473 recognize the next byte after a successfully received address as the command byte (Table 3). Use the command byte to configure the MAX7472/ MAX7473. While most of the commands listed in Table 3 modify the functionality of the MAX7472/ MAX7473, some commands prepare the device for further data transfers (see the Control/Status Register, Frequency Register, and Channel-Selection Register sections.) When the write cycle is prematurely aborted, the register is not updated. Figures 6 and 7 show examples of write sequences.
MAX7472/MAX7473
Command Byte (Write Cycle) A write cycle begins with the bus master issuing a START condition followed by 7 address bits (Figure 5) and a write bit (R/W = 0). After successfully receiving its address, the MAX7472/MAX7473 (slave) issue an
SDA
1 MSB
0
0
1
0
A1
A0 LSB
R/W
ACK
SCL
Figure 5. Slave-Address Byte Definition
SCL
SDA
1
0
0
1
0
A1
A0
R/W
ACK
0 C7
0 C6
0 C5
1 C4 IN
0 C3
0 C2
1 C1
0 C0
ACK
SDA DIRECTION START
IN TO MAX7472/MAX7473
OUT
OUT
SCL (CONT) SDA (CONT) SDA DIRECTION F7 F6 F5 F4 F3 F2 F1 F0 ACK
IN
OUT
IN
STOP COMMAND WORD C7-C0 IS 00010010.
Figure 6. Write Sequence to Update the Frequency Register
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HDTV Anti-Aliasing Filters with Triple-Input Mux MAX7472/MAX7473
Table 3. Command Byte Definition
COMMAND BYTE: INDIVIDUAL BIT DEFINITIONS C7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Power-down. Wake-up; resume normal operation using the frequency/status previously stored (unless power has been cycled). Set clamp voltage level for IN1 to low. Set clamp voltage level for IN1 to high. Set clamp voltage level for IN2 to low. Set clamp voltage level for IN2 to high. Set clamp voltage level for IN3 to low. Set clamp voltage level for IN3 to high. Select component input, color-burst filter disabled. Select composite input, color-burst filter enabled. Select internal sync. Select external sync. Select positive polarity for the external sync. Select negative polarity for the external sync. Enable filters. Disable filters. Enter bypass mode. Reset status to the default status as outlined in the Control/Status register table. This command does not affect the Frequency register and the Channel Selection register. Request reading the Control/Status register. The interface expects an Sr condition to follow with address and read/write set to read so that data can be driven onto the bus. Load the Frequency register with the data byte following the command word. Request reading the Frequency register. The interface expects an Sr condition to follow with address and read/write set to read so that data can be driven onto the bus. Select Input A. Select Input B. Select Input C. Request reading the Channel Selection register. The interface expects an Sr condition to follow with address and read/write set to read so that data can be driven onto the bus. DESCRIPTION
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
1 1 1 1 1 1 1
0 0 0 0 0 0 0
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
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HDTV Anti-Aliasing Filters with Triple-Input Mux MAX7472/MAX7473
SCL SDA 1 0 0 1 0 A1 A0 R/W ACK 0 C7 SDA DIRECTION START COMMAND BITE IS FOR POWER-DOWN. IN TO MAX7472/MAX7473 OUT 0 C6 0 C5 0 C4 IN 0 C3 0 C2 0 C1 0 C0 OUT IN ACK
STOP
Figure 7. Write Sequence for a Command Bite
SCL SDA 1 0 0 1 0 A1 A0 R/W ACK 0 C7 SDA DIRECTION START SCL (CONT) IN TO MAX7472/MAX7473 OUT 0 C6 0 C5 1 C4 IN 0 C3 0 C2 1/0 C1 1 C0 OUT ACK
SDA (CONT) SDA DIRECTION Sr
1
0
0
1
0
A1
A0
R/W
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
IN
OUT
IN
STOP
Figure 8. Basic Read Sequence
Read Cycle In read mode (R/W = 1), the MAX7472/MAX7473 write the contents of the Status, Channel Selection, or Frequency register to the bus. When the command byte indicates a read operation of either the Status or the Frequency register, the serial interface expects an Sr condition to follow the command byte. After sending an Sr, the master sends the MAX7472/MAX7473 slave address byte followed by the R/W bit (set to 1 to indicate a read). The slave device (MAX7472/MAX7473)
generates an ACK for the second address word and immediately after the ACK clock pulse, the direction of data flow reverses. The slave (MAX7472/MAX7473) then transmits 1 byte of data containing the value of the register that was selected in the command byte. Figure 8 shows a basic read sequence. Note: To read the contents of the Status, Channel Selection, or Frequency register, the master must first write a command byte, requesting to read the Status, Channel Selection, or Frequency register.
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HDTV Anti-Aliasing Filters with Triple-Input Mux MAX7472/MAX7473
Control/Status Register The MAX7472/MAX7473 store their status in an 8-bit register that can be read back by the master. The individual bits of the Control/Status register are summarized in Tables 4 and 5. The power-on default value of this register is 03h. Frequency Register The frequency response (-3dB passband edge) of the MAX7472/MAX7473 can be continuously varied in 256 linear steps by changing the codes in the Frequency register (Table 6). See the Command Byte (Write Cycle) section for a write sequence to update the Frequency register.
Table 4. Control/Status Register
CONTROL/STATUS REGISTER S7 S6 S5 S4 S3 S2 S1 S0
Table 5. Control/Status Register Bit Description
BIT S7 S6 S5 S4 S3 S2 S1 S0 DESCRIPTION 0 = component input signal selected (default). 1 = composite input signal selected. 0 = internal sync enabled (default). 1 = external sync enabled. 0 = external sync: positive polarity (default). 1 = external sync: negative polarity. 0 = normal operation mode (default). 1 = power-down mode. 0 = filters enabled (default). 1 = bypass mode--no filtering. 0 = clamp voltage for IN1 set to low (default). 1 = clamp voltage for IN1 set to high. 0 = clamp voltage for IN2 set to low. 1 = clamp voltage for IN2 set to high (default). 0 = clamp voltage for IN3 set to low. 1 = clamp voltage for IN3 set to high (default).
Table 6. Suggested Frequency Register Setting for Various Video-Signal Formats
VIDEO-SIGNAL FORMAT Standard-Definition Interlaced Standard-Definition Progressive High-Definition Low Bandwidth High-Definition High Bandwidth F7 F6 F5 F4 F3 F2 F1 F0 CODE NUMBER APPROXIMATE FREQUENCY (-3dB) (MHz) 10 15 30 34 (default)
0 0 1 1
0 1 1 1
1 0 0 1
0 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
0 0 0 1
40 90 220 255
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HDTV Anti-Aliasing Filters with Triple-Input Mux MAX7472/MAX7473
Table 7. Channel-Selection Register
CHANNEL-SELECTION REGISTER CS7 0 0 1 CS6 0 1 0 CS5 X X X CS4 X X X CS3 X X X CS2 X X X CS1 X X X CS0 X X X DESCRIPTION Channel A selected (default). Channel B selected. Channel C selected.
X = Don't care.
Channel-Selection Register The MAX7472/MAX7473 store channel selection in an 8-bit register that can be read back by the master. The individual bits of the Channel Selection register are summarized in Table 7. The power-on default selects channel A. I2C Compatibility The MAX7472/MAX7473 are compatible with existing I2C systems supporting standard I2C 8-bit communications. The general call address is ignored, and CBUS formats are not supported. The devices' address is compatible with 7-bit I 2C addressing protocol only. Ten-bit address formats are not supported.
matched video cable, ensuring the external resistance determines the termination impedance.
Output Considerations
The MAX7472/MAX7473 outputs can be DC- or ACcoupled. The MAX7473, with +6dB gain, is typically connected to a 75 series back-match resistor followed by the video cable. Because of the inherent divide-by-two of this configuration, the blanking level of the video signal is always less than 1V, which complies with digital TV requirements. The MAX7472, with 0dB gain, is typically connected to an ADC or video decoder. This can be a DC or AC connection. If a DC connection is used, ensure that the DC input requirements of the ADC or video decoder are compatible. When using an AC connection, choose an AC-coupling capacitor value that ensures that the lowest frequency content in the video signal is passed and the line-time distortion is kept within desired limits. The selection of this value is a function of the input impedance and more importantly, the input leakage of the circuit being driven. Use a video clamp to reestablish the DC level if not already included in the subsequent circuit. The outputs of the MAX7472/MAX7473 are fully protected against short-circuit conditions either to ground or to the positive supply of the device.
Applications Information
Input Considerations
Use 0.1F ceramic capacitors to AC-couple the inputs. The input cannot be DC-coupled. The internal clamp circuit stores a DC voltage across the input capacitors to obtain the appropriate output DC voltage level. Increasing the value of these capacitors to improve line-time distortion is not necessary due to the extremely low input leakage current yielding a very low line-time distortion performance. The MAX7472/MAX7473 provide a high input impedance to allow a nonzero source impedance to be used such as when the input is connected directly to a back-
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HDTV Anti-Aliasing Filters with Triple-Input Mux MAX7472/MAX7473
Power-Supply Bypassing and Layout Considerations
The MAX7472/MAX7473 operate from a single +5V analog supply and +3.3V digital supply. Bypass each AVDD to AGND with a 0.1F capacitor with an additional 1F capacitor in parallel for low-frequency decoupling. Determine the proper power-supply bypassing necessary by taking into account the desired disturbance level tolerable on the output, the power-supply rejection of the MAX7472/MAX7473, and the amplitude and frequency of the disturbance signals present in the vicinity of the MAX7472/MAX7473. Use an extensive ground plane to ensure optimum performance. The three AVDD inputs (pins 18, 20, and 22) that supply the individual channels can be connected together and bypassed as one provided the components are close to the pins. Bypass DVDD to DGND with a 0.1F capacitor. Connect all ground pins to a low-impedance ground plane as close to the device as possible. Place the input termination resistors as close to the device as possible. Alternatively, the terminations can be placed further from the device if the PC board traces are designed to be a controlled impedance of 75. Minimize parasitic capacitance as much as possible to avoid performance degradation in the upper frequency range possible with the MAX7472/MAX7473. Refer to the MAX7472/MAX7473 evaluation kit for a proven PC board layout.
Exposed Pad and Heat Dissipation
The MAX7472/MAX7473 TQFN package provides an exposed pad on the bottom side of the package. This pad is electrically connected to AGND and must be soldered to the ground plane for proper thermal conductivity. Do not route any PC board traces under the package. The MAX7472/MAX7473 typically dissipate 900mW of power; therefore, pay attention to heat dispersion. Use at least a two-layer board with a good ground plane. To maximize heat dispersion, place copper directly under the MAX7472/MAX7473 package to match the outline of the plastic encapsulated area. Repeat the same with the bottom ground plane layer and place as many vias as possible connecting the top and bottom layers to thermally connect to the ground plane. Maxim has evaluated a four-layer board using FR-4 material and 1oz copper with equal areas of metal on the top and bottom side coincident with the plastic encapsulated areas of the package. The two middle layers are used as power and ground planes. The board has 21, 15-mil, plated-through via holes between top, bottom, and ground plane layers. Thermocouple measurements confirm device temperatures to be safely within maximum limits.
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HDTV Anti-Aliasing Filters with Triple-Input Mux
Typical Operating Circuit
AVDD 0.1F INA1 INA2 HD INA3 SYNCA 3 2 PROGRAMMABLE LPF FILTER 5MHz-34MHz 0dB (6dB) BUFFER OUT1 0.1F ADC MUX MUX DVDD
MAX7472/MAX7473
CLAMP
INB1 INB2 VGA INB3 SYNCB
EXT SYNC ENABLE PROGRAMMABLE LPF FILTER 5MHz-34MHz 0dB (6dB) BUFFER OUT2 0.1F ADC
MUX
CLAMP/ BIAS
INC1 INC2 SD INC3 SYNCC CLAMP LEVEL I2C INTERFACE BYPASS CLAMP/ BIAS MUX PROGRAMMABLE LPF FILTER 5MHz-34MHz 0dB (6dB) BUFFER OUT3 0.1F ADC
MAX7472 (MAX7473)
SCL SDA AGND () INDICATES THE MAX7473
A1 A0 DGND
Chip Information
PROCESS: BiCMOS
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17
HDTV Anti-Aliasing Filters with Triple-Input Mux MAX7472/MAX7473
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
1 2
18
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HDTV Anti-Aliasing Filters with Triple-Input Mux
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX7472/MAX7473
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
(c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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